VeloceWired® provides a rapid annotation of inductance and magnetic coupling values back into the layout. This is extremely useful as it provides the designer with an immediate "feeling" of what has been drawn so far. Thus the designer can easily quick-fix certain wires that are likely to hinder the circuit's performance (e.g. too long wires that introduce large inductance, parallel wires with undesired magnetic coupling, etc). Without the annotation capability such issues can be detected only by thorough examination of huge netlists, or even after complete circuit simulations are performed
VeloceWired® supports both multi-chip-modules and stacked dies. The design flow remains the same as in the case of creating bondwires from one die to package.
A wide variety of bondwire types is available in VeloceWired. In addition to the widely used jedec-4 and jedec-5 formats, two types of generic format are available. The combination of jedec and generic types allows the user to efficiently approximate practically any type of bondwire (die-package, downdonds, die-die, stacked dies bonding, etc.).
User has the ability to introduce a set of rules for DRC checking. Rules include issues like:
When creating a wire the inductance value appears in the properties definition form. In the case of custom defined wires, after each parameter modification, the button "Calculate L" yields the updated L value. Once the wire is created, the L value appears in the layout at the center point of the wire
Extension of the "Annotation" capability will be the annotation of DC-resistance and mutual inductance. Annotation of resistance will follow the same approach as the inductance. For mutual inductance annotation, the user should be prompted to select the desired pair of wires, before annotation of the Km value is possible.
It is very common in bondwire design, that a slight change in die placement may be necessary. It is vital that the user can have the ability for such die or package movements while maintaining the connectivity between them. In VeloceWired once the new position is defined, the wires are automatically re-drawn and the connectivity previously defined is maintained. The user can instantly have access to the new annotated values and the updated bondwire model.
The bondwire design flow is an easy-to-use, interactive way of creating and modeling a bondwire diagram. The designer should simply bring the die and package instances in a layout view and start graphically placing bondwires in two dimensions. Bondwire profile information is annotated on each wire instance by means of CDF parameters. The bondwire design flow is ideal for cases where a fast - yet accurate - bondwire model is needed for co-simulation with IC circuitry.
Yes, VeloceWired® models consist of RLCk elements that are compatible with any type of RF analysis.
VeloceWired® could run as a standalone tool, however it must have access to the design database (layout and schematic) either in the older format of GDSII files or the newer format which is the OpenAccess initiative supported by almost all the EDA vendors right now.
In practice VeloceWired® must play in concert with a powerful front end environment such as those of Cadence and Mentor, feed the models to a spice-type simulator (Spectre, Eldo, Hspice, ADS, etc) and perform verification for all inductive components in concert with any of the available engines (i.e. Assura, Calibre, etc...)
VeloceWired® is integrated in Cadence Virtuoso flow. So, VeloceWired® can work on every environment that the Cadence IC tools are integrated.
No
The IC suite of tools by Cadence is needed for running VeloceWired in the Cadence Virtuoso® environment. The following Cadence products have to be installed:
No, since everything happens in a span of a few seconds. VeloceWired® added rules do not result in time increase of the RCX job.
Yes. Our layers are placed around inductors for recognition purposes.
A simple viewer is developed that allows the user to have a 3D overview of the resulting bondwire diagram. This feature is extremely useful to correct possible issues like:
VeloceWired® supports one package drawing per project, and any number of die instances (i.e. multi-chip modules). Package 2-D mechanical drawings can be obtained from the package vendor; typically, these come in DXF or/and GDSII formats. If the package is available in GDSII format, user can simply import it through the stream-in procedure found in Cadence, and use at as an instance. For the DXF formats, VeloceWired will incorporate a simple DXF to instance translation procedure.
VeloceWired® features a rapid EM modeling engine, based on closed-form expressions that extract distributed netlists to model the performance of bondwire interconnects. Time-consuming calculations such as matrix inversions have been avoided completely in the algorithm to make it even faster. Furthermore the use of analytic closed-form solutions for the modeling of bondwires makes VeloceRaptor modeler several orders of magnitude faster than any generic EM solver.
The modeling engine of VeloceWired® is based on a set of algorithms derived from EM theory, so the models are very detailed and accurate. Every bondwire is segmented into smaller segments and each segment is modeled using closed-form expressions derived from EM-analysis. The magnetic and capacitive coupling of all segments is then calculated to cover the full phenomenon
VeloceWired® is not a generic EM-Solver. It is focused in the modeling of bondwire interconnects. Using a wide-variety of bondwire model types (jedec and generic format) it can efficiently model a wide variety of bondwire arrays including downbonds, die-die and stacked-die bondwire interconnects. In (rare) cases where bondwires strongly interact with other critical topology elements (e.g. slot antenna) then the use of a full-EM solver is necessary.
VeloceWired® features a rapid EM modeling engine, based on closed-form expressions that extract distributed netlists to model the performance of bondwire interconnects. These expressions take into consideration the package effects inherently. Thus there is no need sidewalls or boundary conditions that are necessary for numerical electromagnetic calculations.
No. VeloceWired® is acting rather synergistically than competitively with Momentum and Assura. VeloceWired® complements these tools with the smart and efficient synthesis capability for wirebonds, as well as with the rapid bondwire modeling engine. The significant reduction in modeling time that VeloceWired® offers, gives to the designers - for the first time - the ability to perform co-simulation of high-speed circuitry with the bondwires, in seconds rather than hours that are needed with the conventional EM modeling tools.
Momentum on the other hand is perfect for the modeling of arbitrary shapes, and ground planes.
Yes. Bondwires are modeled using RLCk lumped elements. Mutual inductance (k elements) is extracted among all bondwires and bondwire segments. The netlists are fully passive, i.e. dependent voltage or current sources are not used.
Yes! VeloceWired® takes into account the increasing resistance by including in the netlist a 3-step ladder network for each segments that effectively models the increasing resistance over frequency
Yes. A VeloceWired® bondwire model will yield an inductance ('L') curve that is frequency-dependent, exhibiting one or more resonance frequencies. Moreover, skin effect is taken into account at higher frequencies.
Bondwire segments are represented as vectors in the 3D space. The 3D geometry is transformed into the 2D space and a full RLCk model is extracted using an enhanced version of VeloceRaptor® modeling engine. The modeling methodology captures complex electromagnetic effects such as self and mutual inductances, frequency-dependent resistance and capacitive coupling.
There is no known limitation for mutual coupling accuracy even for bondwires that are placed farther apart.
The inductances sign is determined by the convention made by the user regarding the current flow.
The maximum frequency based on measured data given to Helic up to date is 40GHz. Helic is very confident of the accuracy of its models.
Yes, the presenece of mould dielectric is taken into account in the modeling process. For each model type that is defined, the dielectric constant value for the surrounding space can be modified, to reflect the presence of injected mould dielectric between bondwires.
Downbonding capability is fully supported in VeloceWired®. Downbonds are treated like any other bondwire, to ensure common behavior during the "Move & Redraw" procedure. They can be set to ground by grounding the respective pins generated in the schematic view
The ground reference is defined as a horizontal ground plane. The relative position of the ground plane to the bondwires is defined by the h3 parameter in the bondwire-model definition procedure.
It is very easy to make VeloceWired® seamlessly integrated into the Cadence IC design flow. User has only to add some parameters to the user's environment and working directory. Velocewired installation procedure is independent to the PDK that user has.
The standard licensing scheme is floating license key checked by a Macrovision FLEXnet® daemon (binary supplied by Helic). The VeloceWired menu in CIW provides manual check-out/check-in for VeloceWired license. A VeloceWired license key gives access to all program features.
For software support requiring on-site work, Helic can dispatch engineering personnel to implement the update at the Customer's premises. We can provide a fixed amount of on-site calls at no additional cost (e.g. 4 per year), as part of our maintenance package. For any additional requests, Helic shall charge with our standard hourly rate plus travel expenses from Europe.
VeloceWired® comprises several modules coded in different programming languages.
The modeler (VeloceRaptor) is coded in C++, with open source libraries employed for specific math functions. Cadence SKILL is used for bondwires source, Cadence Virtuoso GUI and interfaces to other Cadence tools (such as Assura). Finally, portions of TCL code implement various auxiliary functions in the flow.
Specific custom intermediate data files are used for enabling data flow between VeloceWired® modules (e.g. geometry export from Virtuoso to the VeloceRaptor modeler, process stack up file etc.). These files are mostly ASCII format and their structure is generally straightforward.
Helic uses a version-controlled system (SVN) for storing and maintaining developed software assets. Program Change Requests (PCRs), internal documentation and other collateral material are stored in the company's intranet.
Every evolution in the modeling engine is validated against a set of 'golden data'. There is a significant variety of data, provided by foundry and IDM customers; however Helic follows a methodology for ensuring the reliability of the measurements.
Helic has a team of 10 senior engineers with IC design background, assigned to Applications Engineering and Technical Support. Telephone support during Central European office hours and next-day email support are provided. When necessary, Helic can also support customers with web-based online sessions, assist with simulating and verifying customer designs using own resources, provide design support related to the use of VeloceWired®, participate in customer design reviews, etc.
