How does VeloceRF's accuracy compare to electromagnetic (EM) modeling software?
VeloceRF's modeling engine is based on a set of algorithms derived from EM theory, so the models are very detailed and accurate. Being able to efficiently model the effect of lossy substrates, VeloceRF's spiral inductor models actually provide superior silicon accuracy than conventional EM tools. VeloceRF is also orders of magnitude faster than any generic EM solver, since it employs analytic closed-form solutions for the calculation of on-chip inductance.
Which kinds of IC designs/frequency ranges is VeloceRF applicable to?
VeloceRF can significantly enhance the design flow and enable first-silicon success for radio -frequency ICs (RFICs), millimeter-wave ICs (MMICs), systems-in-package, MEMS ICs, RF modules, optoelectronic front-end ICs and, in general, for any kind of chip or module operating in a frequency from few hundred MHz up to 30 GHz, where metal track inductance plays a role.
Is VeloceRF an analysis or synthesis design tool?
Both. VeloceRF is powered by an extremely fast inductance extractor that models spirals, transformers and arbitrary metal tracks in your RFIC/optical IC layout. This makes it an analysis/extraction tool. However, the built-in Spiral Wizard™ function is a versatile layout aid for quickly synthesizing spiral inductor structures that fit certain criteria (e.g. inductance at a particular frequency).
Regarding RF interconnect, does VeloceRF automatically extract inductance from the layout?
VeloceRF works on RF interconnect lines chosen by the designer and converted through the built-in Path2Inductor routine. This gives the designer the flexibility to decide which lines are important for inductance/mutual inductance extraction, and thus avoid generating an overloaded netlist.
Does VeloceRF produce RLCk element netlists?
Yes. Both spirals and interconnect lines are modeled using RLCk lumped elements. Mutual inductance (k elements) are extracted among any type of inductive structure on the IC layout.
Is VeloceRF a 3-D (i.e. multi-layer) modeler?
Yes, VeloceRF can handle spiral inductors and interconnects laid out on all available metalization layers. Mutual inductance is calculated among inductive structures on all layers.
Are VeloceRF models frequency-dependent?
Yes. A VeloceRF inductor model will yield an inductance ("L") curve that is frequency-dependent, exhibiting one or more resonance frequencies. Moreover, skin effect is taken into account at higher frequencies.
Does VeloceRF require parameter-fitting on measured data for a given process?
No. VeloceRF's only input is the process profile, i.e. thickness values and tolerances for the metal layers and intralayer dielectrics, along with substrate properties.
How long does it take VeloceRF to extract the inductance content in a typical RFIC layout?
Some typical examples are provided in the following table:
| Type of cell | Total spiral inductors | Time taken * |
| LNA 5GHz | 12 | 40sec |
| PA 2.5GHz | 14 | 32sec |
| VCO 5GHz | 4 | 4sec |
| I/Q modem | 8 | 15sec |
Should I start working with VeloceRF in Schematic or Layout?
Whichever suits your preference or design stage. You can start building your circuit in the Schematic Editor, and use VeloceRF's Spiral Wizard™ tool to quickly generate inductor symbols with specific L values. Alternatively, you can work in Layout and use either the Spiral Wizard or Create spiral commands, to physically design and customize your inductors. If you are porting designs from past layout work, the Path to Inductor command can help you quickly turn metal paths to VeloceRF-compatible inductors.
Do you support spiral inductor and transformer PCells?
VeloceRF ships with a library of PCells that are compatible with most silicon processes, including square and octagonal, differential and transformer spirals. Customer PCells can be added upon request.
Are VeloceRF models automatically annotated to my design's extracted view?
Yes. In the Virtuoso® layout editor, through a menu command you can generate a single extracted view containing all inductive matter (spirals, RF interconnect, mutual inductances) along with any other drawn devices (transistors, resistors, capacitors, RC parasitics). A single netlist is produced that you can use in simulations.
Will VeloceRF spiral inductors work in LVS (layout-vs-schematic)?
Yes. You may include in your schematic view the symbols generated by VeloceRF for each of your spiral inductors and LVS will work correctly.
Are VeloceRF models compatible with Spectre®RF simulations?
Yes, VeloceRF models consist of RLCk elements that are compatible with any type of RF analysis.
Does VeloceRF handle substrate noise analysis as well?
VeloceRF models the effect of the substrate underneath and around a spiral inductor or RF interconnect line. It's not a full-fledged substrate modeler (yet).
How can VeloceRF help reduce silicon area?
VeloceRF supports arbitrary inductor shapes and aspect ratios and very accurately models their mutual coupling. This enables the designer to optimize inductors for a given area and produce a tightly packed layout. Guidelines imposing minimum inductor-to-inductor clearances may be abandoned, since all inductive interactions can be simulated. In most cases, designing with VeloceRF can save up to 30% of silicon real-estate, compared to conventional inductor design approaches.
How can VeloceRF minimize IC development cycles and costs?
In several ways. First of all, the sheer speed in producing inductor models for complex layouts eliminates the wait usually associated with EM tools. Rapid re-spins of a design in the schematic or post-layout phase are thus made possible. Human error is avoided, since inductor modeling is now part of the physical design flow and there is no need for transferring and stitching models from external simulators. Additionally, since VeloceRF does not require trimming or parameter fitting on measured data, you can design with inductors directly for first-pass success, eliminating the delays and costs of running testchips with inductor "libraries" for characterization and re-use.
How does VeloceRF help in optimizing an RFIC design?
VeloceRF's seamless and highly efficient flow renders inductors and mutual inductances versatile building blocks for RF and high-speed ICs. Using VeloceRF you can generate any arbitrary inductor value, optimized for a given area. This leads to optimal designs. Furthermore, mutual inductances are accurately extracted and can thus be used to good effect, instead of being avoided as detrimental to circuit performance.
Is VeloceRF applicable to system-in-package (SiP)?
Yes, VeloceRF's inductive modeling approach is applicable to multi-layer laminate package substrates, such as LTCC. Contact us to learn more about the VeloceRF SiP add-on, which models SiP modules comprising flip-chip die over a multi-layer laminate. VeloceRF enables the integration of high quality inductors and passive circuitry within the package, and also models the electromagnetic interactions between on-chip and in-package inductive structures.
