Clearly, spending several minutes, hours or even days to model a single spiral inductor is a productivity killer. On the other hand, alternatives such as lookup tables and back-of-the-envelope calculations will not meet your accuracy requirements. A powerful modeling engine now cuts this Gordian knot of on-chip EM simulation, by introducing rapid, lumped element netlist extraction from layout. This robust, vector-based engine was developed specifically for integrated structures, so even the most complex layouts are extracted in seconds. But no compromises in accuracy are made; all applicable electromagnetic effects are covered. Netlist reduction ensures model netlist sizes will not get out of hand.
If you are used to relying on an oracle – or EM guru – for optimal inductors, there is now a better and faster way. If you are the EM guru in your company, your life has just become easier. With Spiral Wizard, part of the VeloceRF toolset, it takes only a few seconds to synthesize an inductor geometry according to your spec. The Spiral Wizard helps you reach an optimal inductor solution effortlessly. It automatically decides on metal stacking and ground shielding options and produces DRC-clean output. Optionally, the Spiral Wizard can shrink the size of the resulting spiral inductor or transformer, helping you save precious real estate.
If you have been using conventional EM solvers for inductor simulation, you have probably been ignoring ground effects. But a spiral inductor is more than a metal coil. On-chip ground is key in determining inductance effects at high frequencies. VeloceRF seamlessly models parasitic effects introduced by substrate contacts around the spiral. This ensures resonance frequencies are correctly predicted, which leads to safer design. Additionally, VeloceRF Pcells support shielding structures that you can use for optimizing the quality factor and isolation properties of spiral inductors.
Making it manufacturable is one thing; being able to model it is another. Design for Manufacturability (DFM) rules impose changes in the structure of spiral inductors and high-speed interconnects that affect their electromagnetic (EM) behaviour. Slotting should be applied to relieve mechanical stress on wide metal tracks. Coverage rules in 90nm and 65nm CMOS impose dummy fill patterns – or confetti – around spiral inductors. VeloceRF supports all this and more, providing Pcells with built-in DFM.You can also simulate the effects of DFM on the EM properties of inductors and interconnects. All of this is performed with great ease and speed.
VeloceRF is taking care of inductors, so that you can focus on designing your circuits. VeloceRF seamlessly interfaces with other tools in your design flow, which makes designing and extracting inductors very straightforward. Verification is greatly enhanced for RF, with inductors being included in layout vs. schematics (LVS) checks. You can extract the whole chip with a single click, taking into account all intentional, parasitic and mutual inductances. Interconnects can easily be extracted in place, so full-chip EM simulation becomes part of the flow.
“VeloceRF is a cool product! It realizes seamless design environment integration in our RFCMOS PDKs. All our RF designers are satisfied from its accuracy and user-friendliness and don’t need to use other complicated tools. We cannot imagine RF-LSI design without VeloceRF!”
“The [+21 dBm] PA met specifications on first pass silicon”
“Our new approach with Helic enables deeper and direct communication with customers on RF design issues in designer's language, other than just a COT library support. Grounding, substrate noise, magnetic coupling are just a few among those critical effects that vary the true performance of RF circuits. Dynamic PDK support reflected in shorter design-time is the key for success.”
“We knew from the start of this project that success depended on executing beyond the state of the art in mixed signal IC design. The engineering collaboration with Helic was instrumental in our first-pass design success. ClariPhy has pioneered the migration to an all-digital 10-Gbit/s PHY, and Helic's tool allowed us to implement our advanced product architecture with confidence.”
“It allows a very fast and seamless inductor implementation”
