Vector-based lumped-element (RLCK) modeling of conductor microstrips. Support for substrate and dielectric losses, conductor skin effect, metal track stacking.
ASCII-type file containing metal, dielectric and substrate thickness and resistivity parameters (typical, min, max). No parameter fitting or preprocessing required.
VeloceRF inductor Pcells, arbitrary path shapes, path-like polygon shapes.
Any SPICE-type simulator.
Square, rectangular, octagonal, circular spiral inductors (single, differential with/without center-tap). Spiral transformers.
Inductance @ frequency, quality factor, size, track width, bridge segment orientation, metal layer stack, polysilicon shield. For transformers: center frequency, bandwidth.
VeloceRules interfaces for layout vs. schematic verification
Spiral inductor instances have layout, symbol and schematic views to support LVS. For post-layout verification, an extracted view is generated, encapsulating a netlist model for all inductors and any mutual inductances. Metal or polysilicon interconnects and arbitrary paths from layout can be interactively included in the extracted view model.
Cadence Assura & Diva, Mentor Calibre, Synopsys Hercules. Additional tools with standard interfaces (e.g. CDL, GDSII) can be supported.
Spiral inductor connectivity, spiral type, size, number of turns, track width, polysilicon shield (on/off), stacking profile.
x86 based PC (Intel/AMD)
Sun Sparc workstations
HP RISC workstations
Linux: RedHat 8 / 9 / EL3, SuSE 9.3 / SLES9
SunOS/Solaris: 8 / 9
HPUX: 11.00 / 11.11
Windows 2000/XP
(VeloceRaptor modeling engine only)
Cadence IC 5.0.33 or higher
AWR Analog Office *
